Nonvolatile semiconductor memory device

This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable res...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: ICHIGE, MASAYUKI
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator ICHIGE, MASAYUKI
description This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI511138BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI511138BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI511138BB3</originalsourceid><addsrcrecordid>eNrjZFD3y88ry89JLMnMSVUoTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxIeGepoaGhsYWTk7GRCgBAKEpKJE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Nonvolatile semiconductor memory device</title><source>esp@cenet</source><creator>ICHIGE, MASAYUKI</creator><creatorcontrib>ICHIGE, MASAYUKI</creatorcontrib><description>This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.</description><language>chi ; eng</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151201&amp;DB=EPODOC&amp;CC=TW&amp;NR=I511138B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151201&amp;DB=EPODOC&amp;CC=TW&amp;NR=I511138B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ICHIGE, MASAYUKI</creatorcontrib><title>Nonvolatile semiconductor memory device</title><description>This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD3y88ry89JLMnMSVUoTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxIeGepoaGhsYWTk7GRCgBAKEpKJE</recordid><startdate>20151201</startdate><enddate>20151201</enddate><creator>ICHIGE, MASAYUKI</creator><scope>EVB</scope></search><sort><creationdate>20151201</creationdate><title>Nonvolatile semiconductor memory device</title><author>ICHIGE, MASAYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI511138BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2015</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>ICHIGE, MASAYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ICHIGE, MASAYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Nonvolatile semiconductor memory device</title><date>2015-12-01</date><risdate>2015</risdate><abstract>This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_TWI511138BB
source esp@cenet
subjects ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
title Nonvolatile semiconductor memory device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T05%3A25%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ICHIGE,%20MASAYUKI&rft.date=2015-12-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI511138BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true