Memory with level shifting word line driver and method thereof

A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHOWDHURY-NAGLE, SHAHNAZ P, PELLEY, PERRY H, LISTON, THOMAS W
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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