Method of forming a bond pad on an i/c chip and resulting structure
A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conduc...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | VOLANT, RICHARD P SRIVASTAVA, KAMALESH K FANTI, LISA A PETRARCA, KEVIN S KNARR, RANDOLPH F EICHSTADT, DAVID E GRIFFITH, JONATHAN H QUON, ROGER A SAUTER, WOLFGANG KNICKERBOCKER, SARAH H CHENG, TIEN-JEN BIGGS, JULIE C |
| description | A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI317153BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI317153BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI317153BB3</originalsourceid><addsrcrecordid>eNrjZHD2TS3JyE9RyE9TSMsvys3MS1dIVEjKz0tRKEgEiuYpJOYpZOonKyRnZBYA2SkKRanFpTklIHXFJUWlySWlRak8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-JNzT2NDc0NTYycmYCCUAjoIxaQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming a bond pad on an i/c chip and resulting structure</title><source>esp@cenet</source><creator>VOLANT, RICHARD P ; SRIVASTAVA, KAMALESH K ; FANTI, LISA A ; PETRARCA, KEVIN S ; KNARR, RANDOLPH F ; EICHSTADT, DAVID E ; GRIFFITH, JONATHAN H ; QUON, ROGER A ; SAUTER, WOLFGANG ; KNICKERBOCKER, SARAH H ; CHENG, TIEN-JEN ; BIGGS, JULIE C</creator><creatorcontrib>VOLANT, RICHARD P ; SRIVASTAVA, KAMALESH K ; FANTI, LISA A ; PETRARCA, KEVIN S ; KNARR, RANDOLPH F ; EICHSTADT, DAVID E ; GRIFFITH, JONATHAN H ; QUON, ROGER A ; SAUTER, WOLFGANG ; KNICKERBOCKER, SARAH H ; CHENG, TIEN-JEN ; BIGGS, JULIE C</creatorcontrib><description>A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20091111&DB=EPODOC&CC=TW&NR=I317153B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20091111&DB=EPODOC&CC=TW&NR=I317153B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>VOLANT, RICHARD P</creatorcontrib><creatorcontrib>SRIVASTAVA, KAMALESH K</creatorcontrib><creatorcontrib>FANTI, LISA A</creatorcontrib><creatorcontrib>PETRARCA, KEVIN S</creatorcontrib><creatorcontrib>KNARR, RANDOLPH F</creatorcontrib><creatorcontrib>EICHSTADT, DAVID E</creatorcontrib><creatorcontrib>GRIFFITH, JONATHAN H</creatorcontrib><creatorcontrib>QUON, ROGER A</creatorcontrib><creatorcontrib>SAUTER, WOLFGANG</creatorcontrib><creatorcontrib>KNICKERBOCKER, SARAH H</creatorcontrib><creatorcontrib>CHENG, TIEN-JEN</creatorcontrib><creatorcontrib>BIGGS, JULIE C</creatorcontrib><title>Method of forming a bond pad on an i/c chip and resulting structure</title><description>A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD2TS3JyE9RyE9TSMsvys3MS1dIVEjKz0tRKEgEiuYpJOYpZOonKyRnZBYA2SkKRanFpTklIHXFJUWlySWlRak8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-JNzT2NDc0NTYycmYCCUAjoIxaQ</recordid><startdate>20091111</startdate><enddate>20091111</enddate><creator>VOLANT, RICHARD P</creator><creator>SRIVASTAVA, KAMALESH K</creator><creator>FANTI, LISA A</creator><creator>PETRARCA, KEVIN S</creator><creator>KNARR, RANDOLPH F</creator><creator>EICHSTADT, DAVID E</creator><creator>GRIFFITH, JONATHAN H</creator><creator>QUON, ROGER A</creator><creator>SAUTER, WOLFGANG</creator><creator>KNICKERBOCKER, SARAH H</creator><creator>CHENG, TIEN-JEN</creator><creator>BIGGS, JULIE C</creator><scope>EVB</scope></search><sort><creationdate>20091111</creationdate><title>Method of forming a bond pad on an i/c chip and resulting structure</title><author>VOLANT, RICHARD P ; SRIVASTAVA, KAMALESH K ; FANTI, LISA A ; PETRARCA, KEVIN S ; KNARR, RANDOLPH F ; EICHSTADT, DAVID E ; GRIFFITH, JONATHAN H ; QUON, ROGER A ; SAUTER, WOLFGANG ; KNICKERBOCKER, SARAH H ; CHENG, TIEN-JEN ; BIGGS, JULIE C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI317153BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>VOLANT, RICHARD P</creatorcontrib><creatorcontrib>SRIVASTAVA, KAMALESH K</creatorcontrib><creatorcontrib>FANTI, LISA A</creatorcontrib><creatorcontrib>PETRARCA, KEVIN S</creatorcontrib><creatorcontrib>KNARR, RANDOLPH F</creatorcontrib><creatorcontrib>EICHSTADT, DAVID E</creatorcontrib><creatorcontrib>GRIFFITH, JONATHAN H</creatorcontrib><creatorcontrib>QUON, ROGER A</creatorcontrib><creatorcontrib>SAUTER, WOLFGANG</creatorcontrib><creatorcontrib>KNICKERBOCKER, SARAH H</creatorcontrib><creatorcontrib>CHENG, TIEN-JEN</creatorcontrib><creatorcontrib>BIGGS, JULIE C</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>VOLANT, RICHARD P</au><au>SRIVASTAVA, KAMALESH K</au><au>FANTI, LISA A</au><au>PETRARCA, KEVIN S</au><au>KNARR, RANDOLPH F</au><au>EICHSTADT, DAVID E</au><au>GRIFFITH, JONATHAN H</au><au>QUON, ROGER A</au><au>SAUTER, WOLFGANG</au><au>KNICKERBOCKER, SARAH H</au><au>CHENG, TIEN-JEN</au><au>BIGGS, JULIE C</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming a bond pad on an i/c chip and resulting structure</title><date>2009-11-11</date><risdate>2009</risdate><abstract>A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_TWI317153BB |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method of forming a bond pad on an i/c chip and resulting structure |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T05%3A15%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=VOLANT,%20RICHARD%20P&rft.date=2009-11-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI317153BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |