Power reduction in a memory bus interface

A technique includes amplifying data signals from a memory bus interface (16). The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus (20). In some embodiments of the invention, the ampli...

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Hauptverfasser:	YOSEF, NOAM, WILCOX, JEFFREY R
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	YOSEF, NOAM WILCOX, JEFFREY R
description	A technique includes amplifying data signals from a memory bus interface (16). The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus (20). In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Power reduction in a memory bus interface
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