Voltage-controlled analog delay locked loop

An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage control, a fast/slow latch, a phase detector, as well as reset and clock off circuits. The fast/slow latch...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	HEIGHTLEY, JOHN, EATON, STEVE S
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY
Online-Zugang:	Volltext bestellen
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