Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel

The invention relates to a method for forming a transistor structure on a substrate (SOI), the substrate comprising a supporting Si layer (1), a buried insulating layer (2), and a top Si layer (3), the top Si layer having a top layer thickness and comprising a high dopant level, the transistor struc...

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Bibliographische Detailangaben

Hauptverfasser:	PONOMAREV, YOURI V, LOO, JOSINE JOHANNA GERARDA PETRA
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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