Electrical performance enhanced wafer level chip scale package with ground

A method including providing a first substrate having a first bond pad and a second bond pad; forming a subassembly comprising securing a second substrate to the first substrate with a ground layer interposed between the first substrate and the second substrate; forming a first trench in the subasse...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	HUANG, CHENDER, WANG, JONES, CHEN, CHIHIANG, TSAO, PEI-HAW, HUANG, HANK
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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