Method for manufacturing semiconductor integrated circuit device

The present invention is to prevent the breakage and ablation of wiring composing the semiconductor integrated circuit device, such as bitlines on DRAM. The present invention is to deposit the HPD SiO film 34 with high density plasma CVD method on the bitlines BL connecting the source/drain areas (1...

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Bibliographische Detailangaben
Hauptverfasser: ASAKA, KATSUYUKI, HOSHINO, YOSHINORI, FUJIWARA, TSUYOSHI, NARIYOSHI, YASUHIRO, OOMORI, KAZUTOSHI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The present invention is to prevent the breakage and ablation of wiring composing the semiconductor integrated circuit device, such as bitlines on DRAM. The present invention is to deposit the HPD SiO film 34 with high density plasma CVD method on the bitlines BL connecting the source/drain areas (17) of MISFET for selecting memory cells of DRAM memory cells; after conducting rapid thermal annealing (RTA) under 750 DEG C, polishing the surface; then, forming the capacitor C connecting the other source/drain areas (17) of MISFET for selecting memory cells. Thus, even for conducting the RTA for crystallization of SiTa film for the capacitor insulative film composing the capacitor C, the present method can still reduce the film stress applied on the bitlines BL for preventing the breakage and ablation of bitlines BL.