SRAM-cells arrangement and its production method

The SRAM-cells arrangement includes at least six transistors per memory-cell. Four of the transistors form a Flip-Flop and are arranged at the corners of a square. The Flip-Flop is controlled by two of the transistors, these two transistors are arranged adjacently on the opposite corners of a diagonal and are outside the square. The adjacent memory-cells along a word-line can be so arranged that a 1st bit-line and a 2nd bit-line of said adjacent memory-cells are coincident. Said transistors are preferably vertical and arranged on semiconductor-structures (St1, St2, St3, St4, St5, St6), which are generated from a layer-sequence. Two of the transistors with n-doped channel-areas are constructed preferably on two semiconductor-structures (St3, St4) respectively.