A method of reducing loading variation during etch processing
In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.
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| creator | KLUWE, ANDREAS ZELL, THOMAS LIEBMANN, LARS PREIN, FRANK |
| description | In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip. |
| format | Patent |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | A method of reducing loading variation during etch processing |
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