Asynchronous SAR logic
A circuit for detecting metastability in an asynchronous successive approximation register analogue to digital converter; wherein a two-output comparator is arranged to receive first and second input signals, compare the first input signal with the second input signal, and drive one of the first and...
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| creator | HJORTLAND, HAKON ANDRE MICHAELSEN, JORGEN ANDREAS |
| description | A circuit for detecting metastability in an asynchronous successive approximation register analogue to digital converter; wherein a two-output comparator is arranged to receive first and second input signals, compare the first input signal with the second input signal, and drive one of the first and second comparison signals to a set state based on the comparison. A first output terminal is in a set state when the first comparison signal is in a set state. A second output terminal is in a set state when the second comparison signal is in a set state. If a predetermined duration passes after the start of the comparison by the two-output comparator and if the first comparison signal and the second comparison signal are both in the reset state, control logic outputs a set state at both the first output terminal and the second output terminal. This allows metastability of a comparator can be detected in an asynchronous SAR ADC. The control logic can effectively time out the comparison if it reaches the predetermi |
| format | Patent |
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A first output terminal is in a set state when the first comparison signal is in a set state. A second output terminal is in a set state when the second comparison signal is in a set state. If a predetermined duration passes after the start of the comparison by the two-output comparator and if the first comparison signal and the second comparison signal are both in the reset state, control logic outputs a set state at both the first output terminal and the second output terminal. This allows metastability of a comparator can be detected in an asynchronous SAR ADC. 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A first output terminal is in a set state when the first comparison signal is in a set state. A second output terminal is in a set state when the second comparison signal is in a set state. If a predetermined duration passes after the start of the comparison by the two-output comparator and if the first comparison signal and the second comparison signal are both in the reset state, control logic outputs a set state at both the first output terminal and the second output terminal. This allows metastability of a comparator can be detected in an asynchronous SAR ADC. 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A first output terminal is in a set state when the first comparison signal is in a set state. A second output terminal is in a set state when the second comparison signal is in a set state. If a predetermined duration passes after the start of the comparison by the two-output comparator and if the first comparison signal and the second comparison signal are both in the reset state, control logic outputs a set state at both the first output terminal and the second output terminal. This allows metastability of a comparator can be detected in an asynchronous SAR ADC. The control logic can effectively time out the comparison if it reaches the predetermi</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY |
| title | Asynchronous SAR logic |
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