Memory device

According to one embodiment, a memory device includes word lines, bit lines, transistors, capacitors, and a plate line. The transistors include first transistors and second transistors. The first and second transistors are coupled to first and second word lines, respectively. The first and second tr...

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1. Verfasser:	INUKAI, TAKASHI
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
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creator	INUKAI, TAKASHI
description	According to one embodiment, a memory device includes word lines, bit lines, transistors, capacitors, and a plate line. The transistors include first transistors and second transistors. The first and second transistors are coupled to first and second word lines, respectively. The first and second transistors are arranged to alternate each other in a first direction. The bit lines include first to fourth bit lines arranged sequentially in the first direction. The first and third bit lines are coupled to the other end of the first and second transistors. The second bit line is coupled to the other end of the first transistors and is not coupled to the other end of the second transistors. The fourth bit line is coupled to the other end of the second transistors and is not coupled to the other end of the first transistors.
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The first and second transistors are arranged to alternate each other in a first direction. The bit lines include first to fourth bit lines arranged sequentially in the first direction. The first and third bit lines are coupled to the other end of the first and second transistors. The second bit line is coupled to the other end of the first transistors and is not coupled to the other end of the second transistors. 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The transistors include first transistors and second transistors. The first and second transistors are coupled to first and second word lines, respectively. The first and second transistors are arranged to alternate each other in a first direction. The bit lines include first to fourth bit lines arranged sequentially in the first direction. The first and third bit lines are coupled to the other end of the first and second transistors. The second bit line is coupled to the other end of the first transistors and is not coupled to the other end of the second transistors. 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The transistors include first transistors and second transistors. The first and second transistors are coupled to first and second word lines, respectively. The first and second transistors are arranged to alternate each other in a first direction. The bit lines include first to fourth bit lines arranged sequentially in the first direction. The first and third bit lines are coupled to the other end of the first and second transistors. The second bit line is coupled to the other end of the first transistors and is not coupled to the other end of the second transistors. The fourth bit line is coupled to the other end of the second transistors and is not coupled to the other end of the first transistors.</abstract><oa>free_for_read</oa></addata></record>
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language	chi ; eng
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subjects	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
title	Memory device
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