Power management chip and operating method thereof

A power management chip includes a gate driver configured to output a first gate signal driving a first power switch and a second gate signal driving the second power switch, a multiplexer configured to receive an error detect signal from a first error amplifier and a first gate signal from the gate...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KIM, MIN-JAE, LEE, YUN-HO, GWON, HUI-DONG, YANG, JUN-HYEOK, KONG, TAE-HWANG
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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