Chip package structure
Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The...
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| Format: | Patent |
| Sprache: | chi ; eng |
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| Zusammenfassung: | Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The redistribution structure includes a first redistribution structure portion physically and electrically connected to the first semiconductor die, a second redistribution structure portion physically and electrically connected to the second semiconductor die, and a dummy bump region positioned between and electrically isolated from the first redistribution structure portion and the second redistribution structure portion. |
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