Speed detection circuit and associated chip

The present invention provides a speed detection circuit including a test signal generator, a launch flip-flop, a device under test (DUT), a capture flip-flop, a comparator and a control circuit. The test signal generator is configured to generate a test signal with a specific pattern. The launch flip-flop is configured to use a first clock signal to sample the test signal to generate a sampled clock signal. The DUT is configured to receive the sampled test signal to generate a delayed test signal. The capture flip-flop is configured to use a second clock signal to sample the delayed test signal to generate an output signal. The comparator is configured to determine if the output signal matches the specific pattern to generate a comparison result. The control circuit is configured to determine a speed of a chip according to the comparison result.