Semiconductor structures and methods of formation

Semiconductor structures and methods of formation

Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.

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Hauptverfasser: KUO, CHIA-PANG, LIU, YAO-MIN, LEE, YA-LIEN, CHEN, KUANIA, CHIN, SHUNG, PENG, HSIN-YING, HUANG, JAU-JIUN, CHI, CHIHIEN
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator KUO, CHIA-PANG
LIU, YAO-MIN
LEE, YA-LIEN
CHEN, KUANIA
CHIN, SHUNG
PENG, HSIN-YING
HUANG, JAU-JIUN
CHI, CHIHIEN
description Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.
format Patent
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor structures and methods of formation
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