Controller in microprocessor and method of performing the same

A controller in a microprocessor and a method of performing the same are provided. In an embodiment, the controller in the microprocessor configured to manage access to dynamic random-access memory (DRAM). The controller includes a first table configured to track cache lines to which zeros have been written for a plurality of first memory regions. The controller includes a second table configured to track cache lines to which zeros have been written for a plurality of second memory regions. Wherein each second memory area of the plurality of second memory areas includes a group of a plurality of first memory areas. Wherein all cache memory lines in each of the plurality of first memory regions in the group have been written with zeros.