Formation of cavity spacer and source-drain epitaxial growth for scaling of gate-all-around transistors

Formation of cavity spacer and source-drain epitaxial growth for scaling of gate-all-around transistors

Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately fo...

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Hauptverfasser: DAS, RITESH K, HSU, WILLIAM, GUHA, BISWAJEET, THIRTHA, VIVEK, GOLONZKA, OLEG, HASAN, MOHAMMAD, KUMAR, NITESH
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.