Semiconductor structure
A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewa...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | LIN, CHI-FENG CHIN, SHUNG CHI, CHIHIEN |
description | A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW202322200A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW202322200A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW202322200A3</originalsourceid><addsrcrecordid>eNrjZBAPTs3NTM7PSylNLskvUiguKQIySotSeRhY0xJzilN5oTQ3g6Kba4izh25qQX58anFBYnJqXmpJfEi4kYGRsZGRkYGBozExagACdiJ8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor structure</title><source>esp@cenet</source><creator>LIN, CHI-FENG ; CHIN, SHUNG ; CHI, CHIHIEN</creator><creatorcontrib>LIN, CHI-FENG ; CHIN, SHUNG ; CHI, CHIHIEN</creatorcontrib><description>A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230601&DB=EPODOC&CC=TW&NR=202322200A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230601&DB=EPODOC&CC=TW&NR=202322200A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN, CHI-FENG</creatorcontrib><creatorcontrib>CHIN, SHUNG</creatorcontrib><creatorcontrib>CHI, CHIHIEN</creatorcontrib><title>Semiconductor structure</title><description>A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAPTs3NTM7PSylNLskvUiguKQIySotSeRhY0xJzilN5oTQ3g6Kba4izh25qQX58anFBYnJqXmpJfEi4kYGRsZGRkYGBozExagACdiJ8</recordid><startdate>20230601</startdate><enddate>20230601</enddate><creator>LIN, CHI-FENG</creator><creator>CHIN, SHUNG</creator><creator>CHI, CHIHIEN</creator><scope>EVB</scope></search><sort><creationdate>20230601</creationdate><title>Semiconductor structure</title><author>LIN, CHI-FENG ; CHIN, SHUNG ; CHI, CHIHIEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW202322200A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIN, CHI-FENG</creatorcontrib><creatorcontrib>CHIN, SHUNG</creatorcontrib><creatorcontrib>CHI, CHIHIEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIN, CHI-FENG</au><au>CHIN, SHUNG</au><au>CHI, CHIHIEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor structure</title><date>2023-06-01</date><risdate>2023</risdate><abstract>A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_TW202322200A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor structure |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T00%3A37%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIN,%20CHI-FENG&rft.date=2023-06-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW202322200A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |