Method and circuit for scan dump of latch array

Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circu...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	DURAIRAJAN, UMA, ZIAJA, THOMAS A, AMIRTHARAJ, DINESH R
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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