Stacked structure for CMOS image sensors
Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation str...
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creator | HUNG, FENGI CHEN, SHENGAU YAUNG, DUN-NIAN KAO, MIN-FENG KUO, WENANG LIU, JENNG LI, SHENGAN |
description | Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW202230766A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW202230766A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW202230766A3</originalsourceid><addsrcrecordid>eNrjZNAILklMzk5NUSguKSpNLiktSlVIyy9ScPb1D1bIzE1MT1UoTs0rzi8q5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8SHhRgZGRsYG5mZmjsbEqAEArWgoFA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Stacked structure for CMOS image sensors</title><source>esp@cenet</source><creator>HUNG, FENGI ; CHEN, SHENGAU ; YAUNG, DUN-NIAN ; KAO, MIN-FENG ; KUO, WENANG ; LIU, JENNG ; LI, SHENGAN</creator><creatorcontrib>HUNG, FENGI ; CHEN, SHENGAU ; YAUNG, DUN-NIAN ; KAO, MIN-FENG ; KUO, WENANG ; LIU, JENNG ; LI, SHENGAN</creatorcontrib><description>Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220801&DB=EPODOC&CC=TW&NR=202230766A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220801&DB=EPODOC&CC=TW&NR=202230766A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HUNG, FENGI</creatorcontrib><creatorcontrib>CHEN, SHENGAU</creatorcontrib><creatorcontrib>YAUNG, DUN-NIAN</creatorcontrib><creatorcontrib>KAO, MIN-FENG</creatorcontrib><creatorcontrib>KUO, WENANG</creatorcontrib><creatorcontrib>LIU, JENNG</creatorcontrib><creatorcontrib>LI, SHENGAN</creatorcontrib><title>Stacked structure for CMOS image sensors</title><description>Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAILklMzk5NUSguKSpNLiktSlVIyy9ScPb1D1bIzE1MT1UoTs0rzi8q5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8SHhRgZGRsYG5mZmjsbEqAEArWgoFA</recordid><startdate>20220801</startdate><enddate>20220801</enddate><creator>HUNG, FENGI</creator><creator>CHEN, SHENGAU</creator><creator>YAUNG, DUN-NIAN</creator><creator>KAO, MIN-FENG</creator><creator>KUO, WENANG</creator><creator>LIU, JENNG</creator><creator>LI, SHENGAN</creator><scope>EVB</scope></search><sort><creationdate>20220801</creationdate><title>Stacked structure for CMOS image sensors</title><author>HUNG, FENGI ; CHEN, SHENGAU ; YAUNG, DUN-NIAN ; KAO, MIN-FENG ; KUO, WENANG ; LIU, JENNG ; LI, SHENGAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW202230766A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HUNG, FENGI</creatorcontrib><creatorcontrib>CHEN, SHENGAU</creatorcontrib><creatorcontrib>YAUNG, DUN-NIAN</creatorcontrib><creatorcontrib>KAO, MIN-FENG</creatorcontrib><creatorcontrib>KUO, WENANG</creatorcontrib><creatorcontrib>LIU, JENNG</creatorcontrib><creatorcontrib>LI, SHENGAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HUNG, FENGI</au><au>CHEN, SHENGAU</au><au>YAUNG, DUN-NIAN</au><au>KAO, MIN-FENG</au><au>KUO, WENANG</au><au>LIU, JENNG</au><au>LI, SHENGAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Stacked structure for CMOS image sensors</title><date>2022-08-01</date><risdate>2022</risdate><abstract>Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Stacked structure for CMOS image sensors |
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