3D memory device with drain select gate cut and method of forming and operating the same

Embodiments of 3D memory devices and methods of forming and operating the same are disclosed. In an example, the 3D memory device includes memory stacked layers, multiple memory serials, and multiple bit line contacts, and each bit line contact is in contact with one of the corresponding multiple memory serials. The memory stack includes alternating conductive layers and dielectric layers. Each memory serial extends vertically through the memory stack. The conductive layer includes a plurality of drain select gate (DSG) lines configured to control the drain of the plurality of memory serials. Multiple memory serials are divided into multiple regions. In a plan view, multiple regions are the smallest repeating units of the stacked memory layers. Each of the plurality of memory serials is adjacent to at least one of the DSG lines.