Memory device and method of operating the same

A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during a first 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during a first 1 cycle of the clock sig...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LEE, HAE-SUK, RYU, JE-MIN, CHOI, JI-HYUN, YOUN, JAE-YOUN, KWON, YOUNGON
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator LEE, HAE-SUK
RYU, JE-MIN
CHOI, JI-HYUN
YOUN, JAE-YOUN
KWON, YOUNGON
description A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during a first 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during a first 1 cycle of the clock signal, receiving a first precharge command through the row pins during a first 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during a second 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during a second 1 cycle of the clock signal, and receiving a second precharge command through the row pins during a second 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW202134895A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW202134895A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW202134895A3</originalsourceid><addsrcrecordid>eNrjZNDzTc3NL6pUSEkty0xOVUjMS1HITS3JyE9RyE9TyC9ILUosycxLVyjJSFUoTsxN5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8SHhRgZGhsYmFpamjsbEqAEA0AcqTw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Memory device and method of operating the same</title><source>esp@cenet</source><creator>LEE, HAE-SUK ; RYU, JE-MIN ; CHOI, JI-HYUN ; YOUN, JAE-YOUN ; KWON, YOUNGON</creator><creatorcontrib>LEE, HAE-SUK ; RYU, JE-MIN ; CHOI, JI-HYUN ; YOUN, JAE-YOUN ; KWON, YOUNGON</creatorcontrib><description>A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during a first 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during a first 1 cycle of the clock signal, receiving a first precharge command through the row pins during a first 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during a second 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during a second 1 cycle of the clock signal, and receiving a second precharge command through the row pins during a second 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210916&amp;DB=EPODOC&amp;CC=TW&amp;NR=202134895A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210916&amp;DB=EPODOC&amp;CC=TW&amp;NR=202134895A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE, HAE-SUK</creatorcontrib><creatorcontrib>RYU, JE-MIN</creatorcontrib><creatorcontrib>CHOI, JI-HYUN</creatorcontrib><creatorcontrib>YOUN, JAE-YOUN</creatorcontrib><creatorcontrib>KWON, YOUNGON</creatorcontrib><title>Memory device and method of operating the same</title><description>A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during a first 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during a first 1 cycle of the clock signal, receiving a first precharge command through the row pins during a first 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during a second 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during a second 1 cycle of the clock signal, and receiving a second precharge command through the row pins during a second 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDzTc3NL6pUSEkty0xOVUjMS1HITS3JyE9RyE9TyC9ILUosycxLVyjJSFUoTsxN5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8SHhRgZGhsYmFpamjsbEqAEA0AcqTw</recordid><startdate>20210916</startdate><enddate>20210916</enddate><creator>LEE, HAE-SUK</creator><creator>RYU, JE-MIN</creator><creator>CHOI, JI-HYUN</creator><creator>YOUN, JAE-YOUN</creator><creator>KWON, YOUNGON</creator><scope>EVB</scope></search><sort><creationdate>20210916</creationdate><title>Memory device and method of operating the same</title><author>LEE, HAE-SUK ; RYU, JE-MIN ; CHOI, JI-HYUN ; YOUN, JAE-YOUN ; KWON, YOUNGON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW202134895A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE, HAE-SUK</creatorcontrib><creatorcontrib>RYU, JE-MIN</creatorcontrib><creatorcontrib>CHOI, JI-HYUN</creatorcontrib><creatorcontrib>YOUN, JAE-YOUN</creatorcontrib><creatorcontrib>KWON, YOUNGON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE, HAE-SUK</au><au>RYU, JE-MIN</au><au>CHOI, JI-HYUN</au><au>YOUN, JAE-YOUN</au><au>KWON, YOUNGON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory device and method of operating the same</title><date>2021-09-16</date><risdate>2021</risdate><abstract>A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during a first 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during a first 1 cycle of the clock signal, receiving a first precharge command through the row pins during a first 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during a second 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during a second 1 cycle of the clock signal, and receiving a second precharge command through the row pins during a second 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_TW202134895A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Memory device and method of operating the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T02%3A59%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEE,%20HAE-SUK&rft.date=2021-09-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW202134895A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true