Resistive memory and recovery resistance window method of resistive memory cell thereof
A resistive memory and a recovery resistance window method of a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell, wherein the over reset voltage difference fa...
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| Format: | Patent |
| Sprache: | chi ; eng |
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| Zusammenfassung: | A resistive memory and a recovery resistance window method of a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in the reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase the compliance current of the resistive memory cell. During the third period, a reset operation is performed on the resistive memory cell. |
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