Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias
Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | JANG, LINUS BOUCHE, GUILLAUME HU, XIANG WEI, ANDY SEHGAL, AKSHEY KM MAHALINGAM, ANBU SELVAM AUGUR, RODERICK ALAN CHILD JR., CRAIG MICHAEL STEPHENS, JASON EUGENE ZALESKI, MARK PAL, SHYAM PERMANA, DAVID MICHAEL |
| description | Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201843702A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201843702A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201843702A3</originalsourceid><addsrcrecordid>eNrjZIh0SS3LTE4tVijPLMlQSM5IzE1LLdLNSS0uVijLTCxWyC3NKcnULUgsKUktysvMS1dIzEtRyE0tychPKVZIyy8C4VyQOIZWHgbWtMSc4lReKM3NoOjmGuLsoZtakB-fWlyQmJyal1oSHxJuZGBoYWJsbmDkaEyMGgD5lDr3</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias</title><source>esp@cenet</source><creator>JANG, LINUS ; BOUCHE, GUILLAUME ; HU, XIANG ; WEI, ANDY ; SEHGAL, AKSHEY ; KM MAHALINGAM, ANBU SELVAM ; AUGUR, RODERICK ALAN ; CHILD JR., CRAIG MICHAEL ; STEPHENS, JASON EUGENE ; ZALESKI, MARK ; PAL, SHYAM ; PERMANA, DAVID MICHAEL</creator><creatorcontrib>JANG, LINUS ; BOUCHE, GUILLAUME ; HU, XIANG ; WEI, ANDY ; SEHGAL, AKSHEY ; KM MAHALINGAM, ANBU SELVAM ; AUGUR, RODERICK ALAN ; CHILD JR., CRAIG MICHAEL ; STEPHENS, JASON EUGENE ; ZALESKI, MARK ; PAL, SHYAM ; PERMANA, DAVID MICHAEL</creatorcontrib><description>Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181216&DB=EPODOC&CC=TW&NR=201843702A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181216&DB=EPODOC&CC=TW&NR=201843702A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JANG, LINUS</creatorcontrib><creatorcontrib>BOUCHE, GUILLAUME</creatorcontrib><creatorcontrib>HU, XIANG</creatorcontrib><creatorcontrib>WEI, ANDY</creatorcontrib><creatorcontrib>SEHGAL, AKSHEY</creatorcontrib><creatorcontrib>KM MAHALINGAM, ANBU SELVAM</creatorcontrib><creatorcontrib>AUGUR, RODERICK ALAN</creatorcontrib><creatorcontrib>CHILD JR., CRAIG MICHAEL</creatorcontrib><creatorcontrib>STEPHENS, JASON EUGENE</creatorcontrib><creatorcontrib>ZALESKI, MARK</creatorcontrib><creatorcontrib>PAL, SHYAM</creatorcontrib><creatorcontrib>PERMANA, DAVID MICHAEL</creatorcontrib><title>Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias</title><description>Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIh0SS3LTE4tVijPLMlQSM5IzE1LLdLNSS0uVijLTCxWyC3NKcnULUgsKUktysvMS1dIzEtRyE0tychPKVZIyy8C4VyQOIZWHgbWtMSc4lReKM3NoOjmGuLsoZtakB-fWlyQmJyal1oSHxJuZGBoYWJsbmDkaEyMGgD5lDr3</recordid><startdate>20181216</startdate><enddate>20181216</enddate><creator>JANG, LINUS</creator><creator>BOUCHE, GUILLAUME</creator><creator>HU, XIANG</creator><creator>WEI, ANDY</creator><creator>SEHGAL, AKSHEY</creator><creator>KM MAHALINGAM, ANBU SELVAM</creator><creator>AUGUR, RODERICK ALAN</creator><creator>CHILD JR., CRAIG MICHAEL</creator><creator>STEPHENS, JASON EUGENE</creator><creator>ZALESKI, MARK</creator><creator>PAL, SHYAM</creator><creator>PERMANA, DAVID MICHAEL</creator><scope>EVB</scope></search><sort><creationdate>20181216</creationdate><title>Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias</title><author>JANG, LINUS ; BOUCHE, GUILLAUME ; HU, XIANG ; WEI, ANDY ; SEHGAL, AKSHEY ; KM MAHALINGAM, ANBU SELVAM ; AUGUR, RODERICK ALAN ; CHILD JR., CRAIG MICHAEL ; STEPHENS, JASON EUGENE ; ZALESKI, MARK ; PAL, SHYAM ; PERMANA, DAVID MICHAEL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201843702A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JANG, LINUS</creatorcontrib><creatorcontrib>BOUCHE, GUILLAUME</creatorcontrib><creatorcontrib>HU, XIANG</creatorcontrib><creatorcontrib>WEI, ANDY</creatorcontrib><creatorcontrib>SEHGAL, AKSHEY</creatorcontrib><creatorcontrib>KM MAHALINGAM, ANBU SELVAM</creatorcontrib><creatorcontrib>AUGUR, RODERICK ALAN</creatorcontrib><creatorcontrib>CHILD JR., CRAIG MICHAEL</creatorcontrib><creatorcontrib>STEPHENS, JASON EUGENE</creatorcontrib><creatorcontrib>ZALESKI, MARK</creatorcontrib><creatorcontrib>PAL, SHYAM</creatorcontrib><creatorcontrib>PERMANA, DAVID MICHAEL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JANG, LINUS</au><au>BOUCHE, GUILLAUME</au><au>HU, XIANG</au><au>WEI, ANDY</au><au>SEHGAL, AKSHEY</au><au>KM MAHALINGAM, ANBU SELVAM</au><au>AUGUR, RODERICK ALAN</au><au>CHILD JR., CRAIG MICHAEL</au><au>STEPHENS, JASON EUGENE</au><au>ZALESKI, MARK</au><au>PAL, SHYAM</au><au>PERMANA, DAVID MICHAEL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias</title><date>2018-12-16</date><risdate>2018</risdate><abstract>Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_TW201843702A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T13%3A15%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JANG,%20LINUS&rft.date=2018-12-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW201843702A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |