System and method for generation of wafer inspection critical areas
A method includes receiving one or more sets of wafer data, identifying one or more primitives from one or more shapes in one or more layers in the one or more sets of wafer data, classifying each of the one or more primitives as a particular primitive type, identifying one or more primitive charact...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | KULKARNI, ASHOK V MANEPALLI, RAJESH UPPALURI, PRASANTI KIRKLAND, JOHN BANERJEE, SAIBAL |
| description | A method includes receiving one or more sets of wafer data, identifying one or more primitives from one or more shapes in one or more layers in the one or more sets of wafer data, classifying each of the one or more primitives as a particular primitive type, identifying one or more primitive characteristics for each of the one or more primitives, generating a primitive database of the one or more primitives, generating one or more rules based on the primitive database, receiving one or more sets of design data, applying the one or more rules to the one or more sets of design data to identify one or more critical areas, and generating one or more wafer inspection recipes including the one or more critical areas for an inspection sub-system. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201834098A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201834098A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201834098A3</originalsourceid><addsrcrecordid>eNrjZHAOriwuSc1VSMxLUchNLcnIT1FIyy9SSE_NSy1KLMnMz1PIT1MoT0xLLVLIzCsuSE0GiyUXZZZkJifmKCQWpSYW8zCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxGSgaSXxIeFGBoYWxiYGlhaOxsSoAQCAWzKt</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>System and method for generation of wafer inspection critical areas</title><source>esp@cenet</source><creator>KULKARNI, ASHOK V ; MANEPALLI, RAJESH ; UPPALURI, PRASANTI ; KIRKLAND, JOHN ; BANERJEE, SAIBAL</creator><creatorcontrib>KULKARNI, ASHOK V ; MANEPALLI, RAJESH ; UPPALURI, PRASANTI ; KIRKLAND, JOHN ; BANERJEE, SAIBAL</creatorcontrib><description>A method includes receiving one or more sets of wafer data, identifying one or more primitives from one or more shapes in one or more layers in the one or more sets of wafer data, classifying each of the one or more primitives as a particular primitive type, identifying one or more primitive characteristics for each of the one or more primitives, generating a primitive database of the one or more primitives, generating one or more rules based on the primitive database, receiving one or more sets of design data, applying the one or more rules to the one or more sets of design data to identify one or more critical areas, and generating one or more wafer inspection recipes including the one or more critical areas for an inspection sub-system.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180916&DB=EPODOC&CC=TW&NR=201834098A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76304</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180916&DB=EPODOC&CC=TW&NR=201834098A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KULKARNI, ASHOK V</creatorcontrib><creatorcontrib>MANEPALLI, RAJESH</creatorcontrib><creatorcontrib>UPPALURI, PRASANTI</creatorcontrib><creatorcontrib>KIRKLAND, JOHN</creatorcontrib><creatorcontrib>BANERJEE, SAIBAL</creatorcontrib><title>System and method for generation of wafer inspection critical areas</title><description>A method includes receiving one or more sets of wafer data, identifying one or more primitives from one or more shapes in one or more layers in the one or more sets of wafer data, classifying each of the one or more primitives as a particular primitive type, identifying one or more primitive characteristics for each of the one or more primitives, generating a primitive database of the one or more primitives, generating one or more rules based on the primitive database, receiving one or more sets of design data, applying the one or more rules to the one or more sets of design data to identify one or more critical areas, and generating one or more wafer inspection recipes including the one or more critical areas for an inspection sub-system.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAOriwuSc1VSMxLUchNLcnIT1FIyy9SSE_NSy1KLMnMz1PIT1MoT0xLLVLIzCsuSE0GiyUXZZZkJifmKCQWpSYW8zCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxGSgaSXxIeFGBoYWxiYGlhaOxsSoAQCAWzKt</recordid><startdate>20180916</startdate><enddate>20180916</enddate><creator>KULKARNI, ASHOK V</creator><creator>MANEPALLI, RAJESH</creator><creator>UPPALURI, PRASANTI</creator><creator>KIRKLAND, JOHN</creator><creator>BANERJEE, SAIBAL</creator><scope>EVB</scope></search><sort><creationdate>20180916</creationdate><title>System and method for generation of wafer inspection critical areas</title><author>KULKARNI, ASHOK V ; MANEPALLI, RAJESH ; UPPALURI, PRASANTI ; KIRKLAND, JOHN ; BANERJEE, SAIBAL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201834098A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KULKARNI, ASHOK V</creatorcontrib><creatorcontrib>MANEPALLI, RAJESH</creatorcontrib><creatorcontrib>UPPALURI, PRASANTI</creatorcontrib><creatorcontrib>KIRKLAND, JOHN</creatorcontrib><creatorcontrib>BANERJEE, SAIBAL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KULKARNI, ASHOK V</au><au>MANEPALLI, RAJESH</au><au>UPPALURI, PRASANTI</au><au>KIRKLAND, JOHN</au><au>BANERJEE, SAIBAL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System and method for generation of wafer inspection critical areas</title><date>2018-09-16</date><risdate>2018</risdate><abstract>A method includes receiving one or more sets of wafer data, identifying one or more primitives from one or more shapes in one or more layers in the one or more sets of wafer data, classifying each of the one or more primitives as a particular primitive type, identifying one or more primitive characteristics for each of the one or more primitives, generating a primitive database of the one or more primitives, generating one or more rules based on the primitive database, receiving one or more sets of design data, applying the one or more rules to the one or more sets of design data to identify one or more critical areas, and generating one or more wafer inspection recipes including the one or more critical areas for an inspection sub-system.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_TW201834098A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | System and method for generation of wafer inspection critical areas |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T12%3A42%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KULKARNI,%20ASHOK%20V&rft.date=2018-09-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW201834098A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |