Computing system and computer-implemented method for designing integrated circuit

A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHO, DA-YEON, WON, HYO-SIG, JANG, MYUNG-SOO, PARK, HYOUN-SOO
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHO, DA-YEON
WON, HYO-SIG
JANG, MYUNG-SOO
PARK, HYOUN-SOO
description A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201833674A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201833674A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201833674A3</originalsourceid><addsrcrecordid>eNrjZAh0zs8tKC3JzEtXKK4sLknNVUjMS1FIBgumFulm5hbkpOam5pWkpijkppZk5KcopOUXKaSkFmem54E0ZQKl0osSQfLJmUXJpZklPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7UkPiTcyMDQwtjYzNzE0ZgYNQBR7jjI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Computing system and computer-implemented method for designing integrated circuit</title><source>esp@cenet</source><creator>CHO, DA-YEON ; WON, HYO-SIG ; JANG, MYUNG-SOO ; PARK, HYOUN-SOO</creator><creatorcontrib>CHO, DA-YEON ; WON, HYO-SIG ; JANG, MYUNG-SOO ; PARK, HYOUN-SOO</creatorcontrib><description>A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks.</description><language>chi ; eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; CALCULATING ; CINEMATOGRAPHY ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180916&amp;DB=EPODOC&amp;CC=TW&amp;NR=201833674A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180916&amp;DB=EPODOC&amp;CC=TW&amp;NR=201833674A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHO, DA-YEON</creatorcontrib><creatorcontrib>WON, HYO-SIG</creatorcontrib><creatorcontrib>JANG, MYUNG-SOO</creatorcontrib><creatorcontrib>PARK, HYOUN-SOO</creatorcontrib><title>Computing system and computer-implemented method for designing integrated circuit</title><description>A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks.</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>CALCULATING</subject><subject>CINEMATOGRAPHY</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAh0zs8tKC3JzEtXKK4sLknNVUjMS1FIBgumFulm5hbkpOam5pWkpijkppZk5KcopOUXKaSkFmem54E0ZQKl0osSQfLJmUXJpZklPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7UkPiTcyMDQwtjYzNzE0ZgYNQBR7jjI</recordid><startdate>20180916</startdate><enddate>20180916</enddate><creator>CHO, DA-YEON</creator><creator>WON, HYO-SIG</creator><creator>JANG, MYUNG-SOO</creator><creator>PARK, HYOUN-SOO</creator><scope>EVB</scope></search><sort><creationdate>20180916</creationdate><title>Computing system and computer-implemented method for designing integrated circuit</title><author>CHO, DA-YEON ; WON, HYO-SIG ; JANG, MYUNG-SOO ; PARK, HYOUN-SOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201833674A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>CALCULATING</topic><topic>CINEMATOGRAPHY</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>CHO, DA-YEON</creatorcontrib><creatorcontrib>WON, HYO-SIG</creatorcontrib><creatorcontrib>JANG, MYUNG-SOO</creatorcontrib><creatorcontrib>PARK, HYOUN-SOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHO, DA-YEON</au><au>WON, HYO-SIG</au><au>JANG, MYUNG-SOO</au><au>PARK, HYOUN-SOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Computing system and computer-implemented method for designing integrated circuit</title><date>2018-09-16</date><risdate>2018</risdate><abstract>A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_TW201833674A
source esp@cenet
subjects APPARATUS SPECIALLY ADAPTED THEREFOR
CALCULATING
CINEMATOGRAPHY
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
title Computing system and computer-implemented method for designing integrated circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T23%3A58%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHO,%20DA-YEON&rft.date=2018-09-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW201833674A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true