Fan-out semiconductor package
A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the s...
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| creator | HARR, KYOUNG-MOO OH, SEUNGUL CHO, YOON-SUK LEE, DOO-HWAN KIM, HYOUNG-JOON OH, KYUNG-SEOB |
| description | A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201810584A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201810584A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201810584A3</originalsourceid><addsrcrecordid>eNrjZJB1S8zTzS8tUShOzc1Mzs9LKU0uyS9SKEhMzk5MT-VhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQFWpeakl8SHhRgaGFoYGphYmjsbEqAEA07IkVw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Fan-out semiconductor package</title><source>esp@cenet</source><creator>HARR, KYOUNG-MOO ; OH, SEUNGUL ; CHO, YOON-SUK ; LEE, DOO-HWAN ; KIM, HYOUNG-JOON ; OH, KYUNG-SEOB</creator><creatorcontrib>HARR, KYOUNG-MOO ; OH, SEUNGUL ; CHO, YOON-SUK ; LEE, DOO-HWAN ; KIM, HYOUNG-JOON ; OH, KYUNG-SEOB</creatorcontrib><description>A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180316&DB=EPODOC&CC=TW&NR=201810584A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180316&DB=EPODOC&CC=TW&NR=201810584A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HARR, KYOUNG-MOO</creatorcontrib><creatorcontrib>OH, SEUNGUL</creatorcontrib><creatorcontrib>CHO, YOON-SUK</creatorcontrib><creatorcontrib>LEE, DOO-HWAN</creatorcontrib><creatorcontrib>KIM, HYOUNG-JOON</creatorcontrib><creatorcontrib>OH, KYUNG-SEOB</creatorcontrib><title>Fan-out semiconductor package</title><description>A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB1S8zTzS8tUShOzc1Mzs9LKU0uyS9SKEhMzk5MT-VhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQFWpeakl8SHhRgaGFoYGphYmjsbEqAEA07IkVw</recordid><startdate>20180316</startdate><enddate>20180316</enddate><creator>HARR, KYOUNG-MOO</creator><creator>OH, SEUNGUL</creator><creator>CHO, YOON-SUK</creator><creator>LEE, DOO-HWAN</creator><creator>KIM, HYOUNG-JOON</creator><creator>OH, KYUNG-SEOB</creator><scope>EVB</scope></search><sort><creationdate>20180316</creationdate><title>Fan-out semiconductor package</title><author>HARR, KYOUNG-MOO ; OH, SEUNGUL ; CHO, YOON-SUK ; LEE, DOO-HWAN ; KIM, HYOUNG-JOON ; OH, KYUNG-SEOB</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201810584A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HARR, KYOUNG-MOO</creatorcontrib><creatorcontrib>OH, SEUNGUL</creatorcontrib><creatorcontrib>CHO, YOON-SUK</creatorcontrib><creatorcontrib>LEE, DOO-HWAN</creatorcontrib><creatorcontrib>KIM, HYOUNG-JOON</creatorcontrib><creatorcontrib>OH, KYUNG-SEOB</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HARR, KYOUNG-MOO</au><au>OH, SEUNGUL</au><au>CHO, YOON-SUK</au><au>LEE, DOO-HWAN</au><au>KIM, HYOUNG-JOON</au><au>OH, KYUNG-SEOB</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Fan-out semiconductor package</title><date>2018-03-16</date><risdate>2018</risdate><abstract>A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Fan-out semiconductor package |
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