Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being di...
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| creator | BOUCHE, GUILLAUME KIM, BYOUNG-YOUP CHILD JR, CRAIG MICHAEL STEPHENS, JASON EUGENE |
| description | A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201735243A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201735243A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201735243A3</originalsourceid><addsrcrecordid>eNqNizsOwkAMRNNQIOAO5gBIkAVRIwSioYtEGZldJ7EIdrRrCm7P8jkA1Yxm3hsXeibrNIA20Gi8s7SAMKAZRXkvwJKrVxHyxirQs1AClACYknpGowD5N5YH2xOuvfpbylpmPnIbvwhHn4FpMWqwTzT75aSYHw_V_rSgQWtKA3oSsrq6lMvV1m3Ktdu5f5gXNyxDgg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit</title><source>esp@cenet</source><creator>BOUCHE, GUILLAUME ; KIM, BYOUNG-YOUP ; CHILD JR, CRAIG MICHAEL ; STEPHENS, JASON EUGENE</creator><creatorcontrib>BOUCHE, GUILLAUME ; KIM, BYOUNG-YOUP ; CHILD JR, CRAIG MICHAEL ; STEPHENS, JASON EUGENE</creatorcontrib><description>A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171001&DB=EPODOC&CC=TW&NR=201735243A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171001&DB=EPODOC&CC=TW&NR=201735243A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOUCHE, GUILLAUME</creatorcontrib><creatorcontrib>KIM, BYOUNG-YOUP</creatorcontrib><creatorcontrib>CHILD JR, CRAIG MICHAEL</creatorcontrib><creatorcontrib>STEPHENS, JASON EUGENE</creatorcontrib><title>Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit</title><description>A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizsOwkAMRNNQIOAO5gBIkAVRIwSioYtEGZldJ7EIdrRrCm7P8jkA1Yxm3hsXeibrNIA20Gi8s7SAMKAZRXkvwJKrVxHyxirQs1AClACYknpGowD5N5YH2xOuvfpbylpmPnIbvwhHn4FpMWqwTzT75aSYHw_V_rSgQWtKA3oSsrq6lMvV1m3Ktdu5f5gXNyxDgg</recordid><startdate>20171001</startdate><enddate>20171001</enddate><creator>BOUCHE, GUILLAUME</creator><creator>KIM, BYOUNG-YOUP</creator><creator>CHILD JR, CRAIG MICHAEL</creator><creator>STEPHENS, JASON EUGENE</creator><scope>EVB</scope></search><sort><creationdate>20171001</creationdate><title>Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit</title><author>BOUCHE, GUILLAUME ; KIM, BYOUNG-YOUP ; CHILD JR, CRAIG MICHAEL ; STEPHENS, JASON EUGENE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201735243A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BOUCHE, GUILLAUME</creatorcontrib><creatorcontrib>KIM, BYOUNG-YOUP</creatorcontrib><creatorcontrib>CHILD JR, CRAIG MICHAEL</creatorcontrib><creatorcontrib>STEPHENS, JASON EUGENE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOUCHE, GUILLAUME</au><au>KIM, BYOUNG-YOUP</au><au>CHILD JR, CRAIG MICHAEL</au><au>STEPHENS, JASON EUGENE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit</title><date>2017-10-01</date><risdate>2017</risdate><abstract>A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit |
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