Dielectric buffer layer

Dielectric buffer layer

Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the pa...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: JEONG, JAMES, LEE, KEVIN J, PATTABHIRAMAN, SRIRAM, TELANG, ADWAIT, MUIRHEAD, JOHN-GERARD
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator JEONG, JAMES
LEE, KEVIN J
PATTABHIRAMAN, SRIRAM
TELANG, ADWAIT
MUIRHEAD, JOHN-GERARD
description Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201731056A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201731056A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201731056A3</originalsourceid><addsrcrecordid>eNrjZBB3yUzNSU0uKcpMVkgqTUtLLVLISaxMLeJhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfEh4UYGhubGhgamZo7GxKgBAMaMIfM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dielectric buffer layer</title><source>esp@cenet</source><creator>JEONG, JAMES ; LEE, KEVIN J ; PATTABHIRAMAN, SRIRAM ; TELANG, ADWAIT ; MUIRHEAD, JOHN-GERARD</creator><creatorcontrib>JEONG, JAMES ; LEE, KEVIN J ; PATTABHIRAMAN, SRIRAM ; TELANG, ADWAIT ; MUIRHEAD, JOHN-GERARD</creatorcontrib><description>Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170901&amp;DB=EPODOC&amp;CC=TW&amp;NR=201731056A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170901&amp;DB=EPODOC&amp;CC=TW&amp;NR=201731056A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JEONG, JAMES</creatorcontrib><creatorcontrib>LEE, KEVIN J</creatorcontrib><creatorcontrib>PATTABHIRAMAN, SRIRAM</creatorcontrib><creatorcontrib>TELANG, ADWAIT</creatorcontrib><creatorcontrib>MUIRHEAD, JOHN-GERARD</creatorcontrib><title>Dielectric buffer layer</title><description>Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBB3yUzNSU0uKcpMVkgqTUtLLVLISaxMLeJhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfEh4UYGhubGhgamZo7GxKgBAMaMIfM</recordid><startdate>20170901</startdate><enddate>20170901</enddate><creator>JEONG, JAMES</creator><creator>LEE, KEVIN J</creator><creator>PATTABHIRAMAN, SRIRAM</creator><creator>TELANG, ADWAIT</creator><creator>MUIRHEAD, JOHN-GERARD</creator><scope>EVB</scope></search><sort><creationdate>20170901</creationdate><title>Dielectric buffer layer</title><author>JEONG, JAMES ; LEE, KEVIN J ; PATTABHIRAMAN, SRIRAM ; TELANG, ADWAIT ; MUIRHEAD, JOHN-GERARD</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201731056A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JEONG, JAMES</creatorcontrib><creatorcontrib>LEE, KEVIN J</creatorcontrib><creatorcontrib>PATTABHIRAMAN, SRIRAM</creatorcontrib><creatorcontrib>TELANG, ADWAIT</creatorcontrib><creatorcontrib>MUIRHEAD, JOHN-GERARD</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JEONG, JAMES</au><au>LEE, KEVIN J</au><au>PATTABHIRAMAN, SRIRAM</au><au>TELANG, ADWAIT</au><au>MUIRHEAD, JOHN-GERARD</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dielectric buffer layer</title><date>2017-09-01</date><risdate>2017</risdate><abstract>Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_TW201731056A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Dielectric buffer layer
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T15%3A38%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JEONG,%20JAMES&rft.date=2017-09-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW201731056A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true