Reducing verification checks when programming a memory device

Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond t...

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Bibliographische Detailangaben

Hauptverfasser:	VAHIDIMOWLAVI, ALLAHYAR, KAVALIPURAPU, KALYAN, YU, ERWIN
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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