Method and system for verifying the design of an integrated circuit, computer readable storage medium

A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic ("LVS") check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respect...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	HUANG, CHI-TING, TSAI, YAO-HSIEN, YEH, CHENG-HUNG, LEE, HSIENHSIN SEAN
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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