Method and system for verifying the design of an integrated circuit, computer readable storage medium

Method and system for verifying the design of an integrated circuit, computer readable storage medium

A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic ("LVS") check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respect...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HUANG, CHI-TING, TSAI, YAO-HSIEN, YEH, CHENG-HUNG, LEE, HSIENHSIN SEAN
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator HUANG, CHI-TING
TSAI, YAO-HSIEN
YEH, CHENG-HUNG
LEE, HSIENHSIN SEAN
description A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic ("LVS") check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201537373A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201537373A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201537373A3</originalsourceid><addsrcrecordid>eNqNyr0KwjAUhuEuDqLew3FX8AdxFlFc3AqOJSZf0gNNUk5Ohd69HbwAeYd3eeYVntA2OzLJURmLIpLPQh8I-5FTIG1BDoVDouwnRpwUQYzCkWWxA-uGbI79oBASGGfeHahoFhNAEY6HuKxm3nQFq98X1fp-q6-PLfrcoPTGIkGb-nXY7U_H89Tl-I_5AhVdP0s</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and system for verifying the design of an integrated circuit, computer readable storage medium</title><source>esp@cenet</source><creator>HUANG, CHI-TING ; TSAI, YAO-HSIEN ; YEH, CHENG-HUNG ; LEE, HSIENHSIN SEAN</creator><creatorcontrib>HUANG, CHI-TING ; TSAI, YAO-HSIEN ; YEH, CHENG-HUNG ; LEE, HSIENHSIN SEAN</creatorcontrib><description>A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic ("LVS") check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151001&amp;DB=EPODOC&amp;CC=TW&amp;NR=201537373A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151001&amp;DB=EPODOC&amp;CC=TW&amp;NR=201537373A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HUANG, CHI-TING</creatorcontrib><creatorcontrib>TSAI, YAO-HSIEN</creatorcontrib><creatorcontrib>YEH, CHENG-HUNG</creatorcontrib><creatorcontrib>LEE, HSIENHSIN SEAN</creatorcontrib><title>Method and system for verifying the design of an integrated circuit, computer readable storage medium</title><description>A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic ("LVS") check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyr0KwjAUhuEuDqLew3FX8AdxFlFc3AqOJSZf0gNNUk5Ohd69HbwAeYd3eeYVntA2OzLJURmLIpLPQh8I-5FTIG1BDoVDouwnRpwUQYzCkWWxA-uGbI79oBASGGfeHahoFhNAEY6HuKxm3nQFq98X1fp-q6-PLfrcoPTGIkGb-nXY7U_H89Tl-I_5AhVdP0s</recordid><startdate>20151001</startdate><enddate>20151001</enddate><creator>HUANG, CHI-TING</creator><creator>TSAI, YAO-HSIEN</creator><creator>YEH, CHENG-HUNG</creator><creator>LEE, HSIENHSIN SEAN</creator><scope>EVB</scope></search><sort><creationdate>20151001</creationdate><title>Method and system for verifying the design of an integrated circuit, computer readable storage medium</title><author>HUANG, CHI-TING ; TSAI, YAO-HSIEN ; YEH, CHENG-HUNG ; LEE, HSIENHSIN SEAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201537373A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>HUANG, CHI-TING</creatorcontrib><creatorcontrib>TSAI, YAO-HSIEN</creatorcontrib><creatorcontrib>YEH, CHENG-HUNG</creatorcontrib><creatorcontrib>LEE, HSIENHSIN SEAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HUANG, CHI-TING</au><au>TSAI, YAO-HSIEN</au><au>YEH, CHENG-HUNG</au><au>LEE, HSIENHSIN SEAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and system for verifying the design of an integrated circuit, computer readable storage medium</title><date>2015-10-01</date><risdate>2015</risdate><abstract>A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic ("LVS") check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_TW201537373A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Method and system for verifying the design of an integrated circuit, computer readable storage medium
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T16%3A54%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HUANG,%20CHI-TING&rft.date=2015-10-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW201537373A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true