Package substrate, semiconductor package and method for forming the same
The invention provides a package substrate, a semiconductor package and a method of forming the same, the package substrate including a substrate body; a first insulating protection layer formed on the surface of the substrate body, wherein the substrate body has a bonding area surrounding the first...
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| creator | CHANG, SHIH-YU TSAI, KUOING |
| description | The invention provides a package substrate, a semiconductor package and a method of forming the same, the package substrate including a substrate body; a first insulating protection layer formed on the surface of the substrate body, wherein the substrate body has a bonding area surrounding the first insulating protection layer defined thereon, and wherein the distance between the outer circumferential side wall of the first insulating protection layer and the bonding area is larger or equal to 0.05mm; and a first circuit layer formed on the surface of the substrate body under the first insulating protection layer and has a plurality of first electrical contact pads formed to extend into the boding area, thereby preventing two adjacent conductive elements from bridging connection due to the formation of air voids and thus increasing good throughput. |
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a first insulating protection layer formed on the surface of the substrate body, wherein the substrate body has a bonding area surrounding the first insulating protection layer defined thereon, and wherein the distance between the outer circumferential side wall of the first insulating protection layer and the bonding area is larger or equal to 0.05mm; and a first circuit layer formed on the surface of the substrate body under the first insulating protection layer and has a plurality of first electrical contact pads formed to extend into the boding area, thereby preventing two adjacent conductive elements from bridging connection due to the formation of air voids and thus increasing good throughput.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140816&DB=EPODOC&CC=TW&NR=201432867A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140816&DB=EPODOC&CC=TW&NR=201432867A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANG, SHIH-YU</creatorcontrib><creatorcontrib>TSAI, KUOING</creatorcontrib><title>Package substrate, semiconductor package and method for forming the same</title><description>The invention provides a package substrate, a semiconductor package and a method of forming the same, the package substrate including a substrate body; a first insulating protection layer formed on the surface of the substrate body, wherein the substrate body has a bonding area surrounding the first insulating protection layer defined thereon, and wherein the distance between the outer circumferential side wall of the first insulating protection layer and the bonding area is larger or equal to 0.05mm; and a first circuit layer formed on the surface of the substrate body under the first insulating protection layer and has a plurality of first electrical contact pads formed to extend into the boding area, thereby preventing two adjacent conductive elements from bridging connection due to the formation of air voids and thus increasing good throughput.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAISEzOTkxPVSguTSouKUosSdVRKE7NzUzOz0spTS7JL1IogCpIzEtRyE0tychPUUgDCgNxbmZeukJJBlBvYm4qDwNrWmJOcSovlOZmUHRzDXH20E0tyI9PLQaakpqXWhIfEm5kYGhibGRhZu5oTIwaAKCpNFk</recordid><startdate>20140816</startdate><enddate>20140816</enddate><creator>CHANG, SHIH-YU</creator><creator>TSAI, KUOING</creator><scope>EVB</scope></search><sort><creationdate>20140816</creationdate><title>Package substrate, semiconductor package and method for forming the same</title><author>CHANG, SHIH-YU ; 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a first insulating protection layer formed on the surface of the substrate body, wherein the substrate body has a bonding area surrounding the first insulating protection layer defined thereon, and wherein the distance between the outer circumferential side wall of the first insulating protection layer and the bonding area is larger or equal to 0.05mm; and a first circuit layer formed on the surface of the substrate body under the first insulating protection layer and has a plurality of first electrical contact pads formed to extend into the boding area, thereby preventing two adjacent conductive elements from bridging connection due to the formation of air voids and thus increasing good throughput.</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
| recordid | cdi_epo_espacenet_TW201432867A |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Package substrate, semiconductor package and method for forming the same |
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