Voltage level shift with interim-voltage-controlled contention interrupt
Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include c...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | MERCHANT, FEROZE A AGARWAL, AMIT KRISHNAMURTHY, RAM K SANNAREDDY, VINOD HSU, STEVEN K |
description | Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area con |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201338423A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201338423A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201338423A3</originalsourceid><addsrcrecordid>eNrjZPAIy88pSUxPVchJLUvNUSjOyEwrUSjPLMlQyMwrSS3KzNUtgyjQTc7PKynKz8lJTVEAMVPzSjLz8yCqikoLSngYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxIuJGBobGxhYmRsaMxMWoAHMk1gw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Voltage level shift with interim-voltage-controlled contention interrupt</title><source>esp@cenet</source><creator>MERCHANT, FEROZE A ; AGARWAL, AMIT ; KRISHNAMURTHY, RAM K ; SANNAREDDY, VINOD ; HSU, STEVEN K</creator><creatorcontrib>MERCHANT, FEROZE A ; AGARWAL, AMIT ; KRISHNAMURTHY, RAM K ; SANNAREDDY, VINOD ; HSU, STEVEN K</creatorcontrib><description>Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area con</description><language>chi ; eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130916&DB=EPODOC&CC=TW&NR=201338423A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130916&DB=EPODOC&CC=TW&NR=201338423A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MERCHANT, FEROZE A</creatorcontrib><creatorcontrib>AGARWAL, AMIT</creatorcontrib><creatorcontrib>KRISHNAMURTHY, RAM K</creatorcontrib><creatorcontrib>SANNAREDDY, VINOD</creatorcontrib><creatorcontrib>HSU, STEVEN K</creatorcontrib><title>Voltage level shift with interim-voltage-controlled contention interrupt</title><description>Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area con</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAIy88pSUxPVchJLUvNUSjOyEwrUSjPLMlQyMwrSS3KzNUtgyjQTc7PKynKz8lJTVEAMVPzSjLz8yCqikoLSngYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxIuJGBobGxhYmRsaMxMWoAHMk1gw</recordid><startdate>20130916</startdate><enddate>20130916</enddate><creator>MERCHANT, FEROZE A</creator><creator>AGARWAL, AMIT</creator><creator>KRISHNAMURTHY, RAM K</creator><creator>SANNAREDDY, VINOD</creator><creator>HSU, STEVEN K</creator><scope>EVB</scope></search><sort><creationdate>20130916</creationdate><title>Voltage level shift with interim-voltage-controlled contention interrupt</title><author>MERCHANT, FEROZE A ; AGARWAL, AMIT ; KRISHNAMURTHY, RAM K ; SANNAREDDY, VINOD ; HSU, STEVEN K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201338423A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>MERCHANT, FEROZE A</creatorcontrib><creatorcontrib>AGARWAL, AMIT</creatorcontrib><creatorcontrib>KRISHNAMURTHY, RAM K</creatorcontrib><creatorcontrib>SANNAREDDY, VINOD</creatorcontrib><creatorcontrib>HSU, STEVEN K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MERCHANT, FEROZE A</au><au>AGARWAL, AMIT</au><au>KRISHNAMURTHY, RAM K</au><au>SANNAREDDY, VINOD</au><au>HSU, STEVEN K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Voltage level shift with interim-voltage-controlled contention interrupt</title><date>2013-09-16</date><risdate>2013</risdate><abstract>Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area con</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_TW201338423A |
source | esp@cenet |
subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | Voltage level shift with interim-voltage-controlled contention interrupt |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T05%3A49%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MERCHANT,%20FEROZE%20A&rft.date=2013-09-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW201338423A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |