Chip package and manufacturing method thereof

An embodiment provides a chip package including a substrate, a cavity extending from an upper surface of substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavit...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	HUANG, CHUN-LUNG, PERNG, BAWING
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
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