Chip package and manufacturing method thereof

Chip package and manufacturing method thereof

An embodiment provides a chip package including a substrate, a cavity extending from an upper surface of substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavit...

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Hauptverfasser: HUANG, CHUN-LUNG, PERNG, BAWING
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator HUANG, CHUN-LUNG
PERNG, BAWING
description An embodiment provides a chip package including a substrate, a cavity extending from an upper surface of substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and a protecting layer covering the chip.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201104810A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201104810A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201104810A3</originalsourceid><addsrcrecordid>eNrjZNB1zsgsUChITM5OTE9VSMxLUchNzCtNS0wuKS3KzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBjUvNSS-JDwo0MDA0NTCwMDRyNiVEDALv8Ki8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Chip package and manufacturing method thereof</title><source>esp@cenet</source><creator>HUANG, CHUN-LUNG ; PERNG, BAWING</creator><creatorcontrib>HUANG, CHUN-LUNG ; PERNG, BAWING</creatorcontrib><description>An embodiment provides a chip package including a substrate, a cavity extending from an upper surface of substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and a protecting layer covering the chip.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110201&amp;DB=EPODOC&amp;CC=TW&amp;NR=201104810A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110201&amp;DB=EPODOC&amp;CC=TW&amp;NR=201104810A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HUANG, CHUN-LUNG</creatorcontrib><creatorcontrib>PERNG, BAWING</creatorcontrib><title>Chip package and manufacturing method thereof</title><description>An embodiment provides a chip package including a substrate, a cavity extending from an upper surface of substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and a protecting layer covering the chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB1zsgsUChITM5OTE9VSMxLUchNzCtNS0wuKS3KzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBjUvNSS-JDwo0MDA0NTCwMDRyNiVEDALv8Ki8</recordid><startdate>20110201</startdate><enddate>20110201</enddate><creator>HUANG, CHUN-LUNG</creator><creator>PERNG, BAWING</creator><scope>EVB</scope></search><sort><creationdate>20110201</creationdate><title>Chip package and manufacturing method thereof</title><author>HUANG, CHUN-LUNG ; PERNG, BAWING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201104810A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HUANG, CHUN-LUNG</creatorcontrib><creatorcontrib>PERNG, BAWING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HUANG, CHUN-LUNG</au><au>PERNG, BAWING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip package and manufacturing method thereof</title><date>2011-02-01</date><risdate>2011</risdate><abstract>An embodiment provides a chip package including a substrate, a cavity extending from an upper surface of substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and a protecting layer covering the chip.</abstract><oa>free_for_read</oa></addata></record>
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language chi ; eng
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Chip package and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T03%3A51%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HUANG,%20CHUN-LUNG&rft.date=2011-02-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW201104810A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true