Power-on initialization and test for a cascade interconnect memory system

A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection thr...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BUCHMANN, PETER L, FERRAIOLO, FRANK D, RETTER, ERIC E, TROMBLEY, MICHAEL R, THOMSEN, PETER M, REESE, ROBERT J, GOWER, KEVIN C, SPEAR, MICHAEL B, SCHMATZ, MARTIN L
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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