IC layout optimization to improve yield

A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MAYNARD, DANIEL N, GRAY, MICHAEL S, WALKER, ROBERT F, CHU, ALBERT M, HIBBELER, JASON, ALLEN, ROBERT J, BAKER, FAYE D, TAN, MERVYN Y
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!