Multiple reference clock synthesizer

A clock synthesizer (100) for dividing a source clock by N.R including a logic circuit, a delay line (103), a select circuit, an accumulator (113), and a clock divider circuit. The logic circuit divides N.R by 2M to get NNEW.RNEW in which NNEW is zero and RNEW is at least 0.5. The delay line receive...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	FLYNN, CINDA L
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY GENERATION OF NOISE BY SUCH CIRCUITS GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER
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