Improved on-chip Cu interconnection using 1 to 5 nm thick metal cap

Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increase the adhesion strength between the Cu and dielectric, and reduce interface diffusion of Cu. In addition, the thin cap layer further increase electromigration Cu lifetime and reduce the stress induced voiding. The elective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.