Unified decoder architecture

Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder, decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	GAURAV AGARWAL, SANE, ANIRUDDA, BLDNUR, RAVINDRA, SHERIGAR, BHASKAR, PAI, LAKSHMIKANTH RAMADAS, BHATIA, SANDEEP
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!