Memory device and method of manufacture
A memory cell and a method for manufacturing the memory cell. The memory cell is constructed so that it has a ratio of a dimension in the direction of the bit lines to a dimension in the direction of the word line of less than one. The bit lines are formed from the first metallization system of the...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | GIESEKE, BRUCE ALAN MCGEE, WILLIAM A MILIC-STRKALJ, OGNJEN |
| description | A memory cell and a method for manufacturing the memory cell. The memory cell is constructed so that it has a ratio of a dimension in the direction of the bit lines to a dimension in the direction of the word line of less than one. The bit lines are formed from the first metallization system of the memory cell, which is the metallization system nearest the surface of the substrate and the silicide regions of the memory cell. The word line is formed from a metallization system above the first metallization system. Thus, the bit lines are positioned vertically between the substrate surface and the word line. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW200541020A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW200541020A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW200541020A3</originalsourceid><addsrcrecordid>eNrjZFD3Tc3NL6pUSEkty0xOVUjMS1HITS3JyE9RyE9TyE3MK01LTC4pLUrlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxIeFGBgamJoYGRgaOxsSoAQCLYifL</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Memory device and method of manufacture</title><source>esp@cenet</source><creator>GIESEKE, BRUCE ALAN ; MCGEE, WILLIAM A ; MILIC-STRKALJ, OGNJEN</creator><creatorcontrib>GIESEKE, BRUCE ALAN ; MCGEE, WILLIAM A ; MILIC-STRKALJ, OGNJEN</creatorcontrib><description>A memory cell and a method for manufacturing the memory cell. The memory cell is constructed so that it has a ratio of a dimension in the direction of the bit lines to a dimension in the direction of the word line of less than one. The bit lines are formed from the first metallization system of the memory cell, which is the metallization system nearest the surface of the substrate and the silicide regions of the memory cell. The word line is formed from a metallization system above the first metallization system. Thus, the bit lines are positioned vertically between the substrate surface and the word line.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20051216&DB=EPODOC&CC=TW&NR=200541020A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20051216&DB=EPODOC&CC=TW&NR=200541020A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GIESEKE, BRUCE ALAN</creatorcontrib><creatorcontrib>MCGEE, WILLIAM A</creatorcontrib><creatorcontrib>MILIC-STRKALJ, OGNJEN</creatorcontrib><title>Memory device and method of manufacture</title><description>A memory cell and a method for manufacturing the memory cell. The memory cell is constructed so that it has a ratio of a dimension in the direction of the bit lines to a dimension in the direction of the word line of less than one. The bit lines are formed from the first metallization system of the memory cell, which is the metallization system nearest the surface of the substrate and the silicide regions of the memory cell. The word line is formed from a metallization system above the first metallization system. Thus, the bit lines are positioned vertically between the substrate surface and the word line.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD3Tc3NL6pUSEkty0xOVUjMS1HITS3JyE9RyE9TyE3MK01LTC4pLUrlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxIeFGBgamJoYGRgaOxsSoAQCLYifL</recordid><startdate>20051216</startdate><enddate>20051216</enddate><creator>GIESEKE, BRUCE ALAN</creator><creator>MCGEE, WILLIAM A</creator><creator>MILIC-STRKALJ, OGNJEN</creator><scope>EVB</scope></search><sort><creationdate>20051216</creationdate><title>Memory device and method of manufacture</title><author>GIESEKE, BRUCE ALAN ; MCGEE, WILLIAM A ; MILIC-STRKALJ, OGNJEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW200541020A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2005</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GIESEKE, BRUCE ALAN</creatorcontrib><creatorcontrib>MCGEE, WILLIAM A</creatorcontrib><creatorcontrib>MILIC-STRKALJ, OGNJEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GIESEKE, BRUCE ALAN</au><au>MCGEE, WILLIAM A</au><au>MILIC-STRKALJ, OGNJEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory device and method of manufacture</title><date>2005-12-16</date><risdate>2005</risdate><abstract>A memory cell and a method for manufacturing the memory cell. The memory cell is constructed so that it has a ratio of a dimension in the direction of the bit lines to a dimension in the direction of the word line of less than one. The bit lines are formed from the first metallization system of the memory cell, which is the metallization system nearest the surface of the substrate and the silicide regions of the memory cell. The word line is formed from a metallization system above the first metallization system. Thus, the bit lines are positioned vertically between the substrate surface and the word line.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_TW200541020A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Memory device and method of manufacture |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T11%3A33%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GIESEKE,%20BRUCE%20ALAN&rft.date=2005-12-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW200541020A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |