Self regulating temperature/performance/voltage scheme for micros (x86)
A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | PRICER WILBUR DAVID VENTRONE SEBASTIAN THEODORE MICHAIL MICHEL SALIB |
| description | A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_SG66414A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>SG66414A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_SG66414A13</originalsourceid><addsrcrecordid>eNrjZHAPTs1JUyhKTS_NSSzJzEtXKEnNLUgtSiwpLUrVBzLS8otyE_OSU_XL8nNKEtNTFYqTM1JzUxWA4gq5mclF-cUKGhUWZpo8DKxpiTnFqbxQmptBzs01xNlDN7UgPz61uCAxOTUvtSQ-2N3MzMTQxNHQmKACAEwoMpI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Self regulating temperature/performance/voltage scheme for micros (x86)</title><source>esp@cenet</source><creator>PRICER WILBUR DAVID ; VENTRONE SEBASTIAN THEODORE ; MICHAIL MICHEL SALIB</creator><creatorcontrib>PRICER WILBUR DAVID ; VENTRONE SEBASTIAN THEODORE ; MICHAIL MICHEL SALIB</creatorcontrib><description>A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990720&DB=EPODOC&CC=SG&NR=66414A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990720&DB=EPODOC&CC=SG&NR=66414A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PRICER WILBUR DAVID</creatorcontrib><creatorcontrib>VENTRONE SEBASTIAN THEODORE</creatorcontrib><creatorcontrib>MICHAIL MICHEL SALIB</creatorcontrib><title>Self regulating temperature/performance/voltage scheme for micros (x86)</title><description>A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAPTs1JUyhKTS_NSSzJzEtXKEnNLUgtSiwpLUrVBzLS8otyE_OSU_XL8nNKEtNTFYqTM1JzUxWA4gq5mclF-cUKGhUWZpo8DKxpiTnFqbxQmptBzs01xNlDN7UgPz61uCAxOTUvtSQ-2N3MzMTQxNHQmKACAEwoMpI</recordid><startdate>19990720</startdate><enddate>19990720</enddate><creator>PRICER WILBUR DAVID</creator><creator>VENTRONE SEBASTIAN THEODORE</creator><creator>MICHAIL MICHEL SALIB</creator><scope>EVB</scope></search><sort><creationdate>19990720</creationdate><title>Self regulating temperature/performance/voltage scheme for micros (x86)</title><author>PRICER WILBUR DAVID ; VENTRONE SEBASTIAN THEODORE ; MICHAIL MICHEL SALIB</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_SG66414A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>PRICER WILBUR DAVID</creatorcontrib><creatorcontrib>VENTRONE SEBASTIAN THEODORE</creatorcontrib><creatorcontrib>MICHAIL MICHEL SALIB</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PRICER WILBUR DAVID</au><au>VENTRONE SEBASTIAN THEODORE</au><au>MICHAIL MICHEL SALIB</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Self regulating temperature/performance/voltage scheme for micros (x86)</title><date>1999-07-20</date><risdate>1999</risdate><abstract>A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_SG66414A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Self regulating temperature/performance/voltage scheme for micros (x86) |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T04%3A33%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PRICER%20WILBUR%20DAVID&rft.date=1999-07-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ESG66414A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |