SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product in...
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| creator | GARG, Ashutosh HAREL, Yoav RANGANATHAN, Vasanth GEORGE, Varghese MAIYURAN, Subramaniam APPU, Abhishek OULD-AHMED-VALL, Elmoustapha SURTI, Prasoonkumar KIM, SungYe HUNTER, JR RAY, Joydeep MACPHERSON, Mike ANDREI, Valentin KOKER, Altug SADLER, William VEMULAPALLI, Vikranth STRIRAMASSARMA, Lakshminarayanan JANUS, Scott |
| description | Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array. |
| format | Patent |
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One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. 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One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE |
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