A METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH
A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO an...
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creator | STOM, GREGORY ALLEN SATO, JUSTIN HIROKI |
description | A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_SG11201702042YA</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>SG11201702042YA</sourcerecordid><originalsourceid>FETCH-epo_espacenet_SG11201702042YA3</originalsourceid><addsrcrecordid>eNrjZHB2VPB1DfHwd1Fw8w9SCPDwD_H38QTy3YMcAzwidd2CXF0Vgl193HQdfTzd_VxdFIJcw1yDgl0VHJ1DPMNcFVxDnD14GFjTEnOKU3mhNDeDihtIXDe1ID8-tbggMTk1L7UkPtjd0NDIwNDcwMjAxCjS0ZhIZQAlTSzQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>A METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH</title><source>esp@cenet</source><creator>STOM, GREGORY ALLEN ; SATO, JUSTIN HIROKI</creator><creatorcontrib>STOM, GREGORY ALLEN ; SATO, JUSTIN HIROKI</creatorcontrib><description>A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170427&DB=EPODOC&CC=SG&NR=11201702042YA$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170427&DB=EPODOC&CC=SG&NR=11201702042YA$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>STOM, GREGORY ALLEN</creatorcontrib><creatorcontrib>SATO, JUSTIN HIROKI</creatorcontrib><title>A METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH</title><description>A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHB2VPB1DfHwd1Fw8w9SCPDwD_H38QTy3YMcAzwidd2CXF0Vgl193HQdfTzd_VxdFIJcw1yDgl0VHJ1DPMNcFVxDnD14GFjTEnOKU3mhNDeDihtIXDe1ID8-tbggMTk1L7UkPtjd0NDIwNDcwMjAxCjS0ZhIZQAlTSzQ</recordid><startdate>20170427</startdate><enddate>20170427</enddate><creator>STOM, GREGORY ALLEN</creator><creator>SATO, JUSTIN HIROKI</creator><scope>EVB</scope></search><sort><creationdate>20170427</creationdate><title>A METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH</title><author>STOM, GREGORY ALLEN ; SATO, JUSTIN HIROKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_SG11201702042YA3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>STOM, GREGORY ALLEN</creatorcontrib><creatorcontrib>SATO, JUSTIN HIROKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>STOM, GREGORY ALLEN</au><au>SATO, JUSTIN HIROKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH</title><date>2017-04-27</date><risdate>2017</risdate><abstract>A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | A METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH |
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