SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED ERROR CORRECTION CIRCUITS THEREIN
An error correction circuit includes an error correction code (ECC) memory and an ECC engine. The ECC memory stores an ECC, which is at least partially represented by a generation matrix. The ECC engine generates parity data based on main data using the ECC, and detects and/or corrects at least one...
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creator | Sanguhn Cha Yesin Ryu |
description | An error correction circuit includes an error correction code (ECC) memory and an ECC engine. The ECC memory stores an ECC, which is at least partially represented by a generation matrix. The ECC engine generates parity data based on main data using the ECC, and detects and/or corrects at least one error bit in the main data read from the memory cell array using the parity data. The main data includes a plurality of data bits divided into a plurality of sub data units. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units. The column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol and the mis-corrected bit is generated due to the multiple error bits in the main data. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_SG10202001791WA</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>SG10202001791WA</sourcerecordid><originalsourceid>FETCH-epo_espacenet_SG10202001791WA3</originalsourceid><addsrcrecordid>eNqNyrEKwjAQgOEsDqK-ww2uQqODOIbL2dzQC1zSFqdSJE6ihfr-2MEHkH_4l29tJFHDGMW3mKNCQ03UG3jqGClBcB1LDSTBCZIHUl0QRlXCzFEAWbHlnCAHUmLZmtVjfM5l9_vG7K-UMRzK9B7KPI338iqfIdW2Oi5V9nyxvTv9yb5gljBO</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED ERROR CORRECTION CIRCUITS THEREIN</title><source>esp@cenet</source><creator>Sanguhn Cha ; Yesin Ryu</creator><creatorcontrib>Sanguhn Cha ; Yesin Ryu</creatorcontrib><description>An error correction circuit includes an error correction code (ECC) memory and an ECC engine. The ECC memory stores an ECC, which is at least partially represented by a generation matrix. The ECC engine generates parity data based on main data using the ECC, and detects and/or corrects at least one error bit in the main data read from the memory cell array using the parity data. The main data includes a plurality of data bits divided into a plurality of sub data units. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units. The column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol and the mis-corrected bit is generated due to the multiple error bits in the main data.</description><language>eng</language><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210128&DB=EPODOC&CC=SG&NR=10202001791WA$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210128&DB=EPODOC&CC=SG&NR=10202001791WA$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Sanguhn Cha</creatorcontrib><creatorcontrib>Yesin Ryu</creatorcontrib><title>SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED ERROR CORRECTION CIRCUITS THEREIN</title><description>An error correction circuit includes an error correction code (ECC) memory and an ECC engine. The ECC memory stores an ECC, which is at least partially represented by a generation matrix. The ECC engine generates parity data based on main data using the ECC, and detects and/or corrects at least one error bit in the main data read from the memory cell array using the parity data. The main data includes a plurality of data bits divided into a plurality of sub data units. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units. The column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol and the mis-corrected bit is generated due to the multiple error bits in the main data.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQgOEsDqK-ww2uQqODOIbL2dzQC1zSFqdSJE6ihfr-2MEHkH_4l29tJFHDGMW3mKNCQ03UG3jqGClBcB1LDSTBCZIHUl0QRlXCzFEAWbHlnCAHUmLZmtVjfM5l9_vG7K-UMRzK9B7KPI338iqfIdW2Oi5V9nyxvTv9yb5gljBO</recordid><startdate>20210128</startdate><enddate>20210128</enddate><creator>Sanguhn Cha</creator><creator>Yesin Ryu</creator><scope>EVB</scope></search><sort><creationdate>20210128</creationdate><title>SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED ERROR CORRECTION CIRCUITS THEREIN</title><author>Sanguhn Cha ; Yesin Ryu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_SG10202001791WA3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Sanguhn Cha</creatorcontrib><creatorcontrib>Yesin Ryu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sanguhn Cha</au><au>Yesin Ryu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED ERROR CORRECTION CIRCUITS THEREIN</title><date>2021-01-28</date><risdate>2021</risdate><abstract>An error correction circuit includes an error correction code (ECC) memory and an ECC engine. The ECC memory stores an ECC, which is at least partially represented by a generation matrix. The ECC engine generates parity data based on main data using the ECC, and detects and/or corrects at least one error bit in the main data read from the memory cell array using the parity data. The main data includes a plurality of data bits divided into a plurality of sub data units. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units. The column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol and the mis-corrected bit is generated due to the multiple error bits in the main data.</abstract><oa>free_for_read</oa></addata></record> |
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title | SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED ERROR CORRECTION CIRCUITS THEREIN |
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