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1509795 Active filters PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 15 April 1975 [18 April 1974] 15404/75 Heading H3U A digital filter comprises: a delay device 8, 9,... to which pulses, derived from an input signal at 1, are applied in accordance with a clock signal on line 14, the delay device being controlled by a signal on line 15 which is an integral multiple of the frequency of the clock signal, so as to produce a train of output pulses in time sequence in response to each input pulse; a digital multiplier 16 coupled to the delay device and to a multiplication programme 23 whereby the pulses of each train are multiplied by successive digital multiplication coefficients to characterize the desired transfer function; and a storage device 34, coupled to the output of the multiplier, which includes a sign reversing device 91, 92, 93,... and a summation device 88, 89, 90,... which, according to a predetermined programme, forms the sum of alternating polarity of the multiplier outputs in given time periods with those of preceding time periods to produce the desired filter output. An input signal at 1 is sampled to produce digitally encoded data which is fed in parallel form to shift register delays 8, 9,... each time the clock signal on line 14 closes the related switch 12, 13,... to the terminals 4, 5,... of encoder 3. During the remainder of each clock period the switches 12, 13, ... close the feedback loop of the delays and the information stored is fed out of them, under the control of the higher frequency signal on line 15, to the multiplier 16 which as shown is of the type described in Specification 1,445,901. The multiplier outputs are then passed to an accumulator 71. Referring to Fig. 2, it is shown that the a band-pass response centred on a low frequency, Fig. 2b has the time transformed response of Fig. 2a whereas a band-pass response centred on a higher frequency, Fig. 2c, has the time transformed response of Fig. 2d, the additional zero crossings implying the need for a higher clock frequency to obtain the same accuracy of response. In the present invention, this need for a higher clock frequency is obviated by the inclusion of the sign reversing and summation devices of unit 68 which in effect modify the response of Fig. 2a to that of Fig. 2d. The parallel outputs from the accumulator are fed to inputs of the respective summation devices 88, 89, 90 and the outputs from these devices are fed via bi-stables 94, 95, 96, ..., which give delays