METHOD OF BIPOLAR TRANSISTOR MANUFACTURING

FIELD: electrics. ^ SUBSTANCE: invention concerns microelectronics and can be applied in bipolar transistor manufacturing technology. Method of bipolar transistor manufacturing involves forming additional local screen layer at the point of future contact to passive base area, forming passive base ar...

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Bibliographische Detailangaben
Hauptverfasser: SAUROV ALEKSANDR NIKOLAEVICH, MANZHA NIKOLAJ MIKHAJLOVICH
Format: Patent
Sprache:eng ; rus
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Zusammenfassung:FIELD: electrics. ^ SUBSTANCE: invention concerns microelectronics and can be applied in bipolar transistor manufacturing technology. Method of bipolar transistor manufacturing involves forming additional local screen layer at the point of future contact to passive base area, forming passive base area under protection of local screen layers, forming third dielectric insulation and first amorphous silicon layer, their planarisation till planarity with second dielectric insulation, etching of third dielectric insulation positioned between first amorphous silicon layer and second dielectric insulation to the depth of first amorphous silicon layer, its planarisation till planarity with second dielectric insulation, forming fourth dielectric insulation over amorphous silicon, removal of second dielectric insulation and screen layers up to first dielectric formed on epitaxial layer, forming third amorphous silicon layer on vertical window walls, removal of first dielectric formed on epitaxial layer, forming polymonocrystalline layer by hydride epitaxy, with monocrystalline silicon cultivated in opened windows and polycrystalline silicon is cultivated over amorphous silicon, planarisation till planarity with third dielectric insulation, local reinforcement of monocrystalline area at the point of passive base area contact and of monocrystalline area at active base area with first conductance type additive, local reinforcement of monocrystalline area at active base area and of monocrystalline area under deep collector contact to hidden layer with second conductance type additive, thermal annealing and forming metal-coated wiring. ^ EFFECT: enhanced compactness of transistor structures, increased output of usable items due to reduced roughness of structure. ^ 10 dwg