Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation
Chip Scale Packages - CSPs - have the electronic circuits on a silicon chip (6). Electrical contact with the chip is made via bump contact points (7) under the chip and above the base carrier (4). After assembly, the package is encapsulated in insulating material. In conventional manufacturing syste...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | dut ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | HENDRIKUS JOHANNES BERNARDUS PETERS WALTER PETER DE MUNNIK |
| description | Chip Scale Packages - CSPs - have the electronic circuits on a silicon chip (6). Electrical contact with the chip is made via bump contact points (7) under the chip and above the base carrier (4). After assembly, the package is encapsulated in insulating material. In conventional manufacturing systems, air can become trapped under the chip, leaving a void (8). In the present method a small vent hole is left in the center of the chip. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_NL1011949CC2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>NL1011949CC2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_NL1011949CC23</originalsourceid><addsrcrecordid>eNqNjTEOwjAQBNNQIOAPRw8SAZrUEYgCqOjRxbkkFs6dZZ_hEXyaoPAAqpV2Z7TT7H1BTg0aTcFyCz1pJzU0EoAcGQ3C1oDprIdo0BF4NA9saQUpUoTYo3MgnvgrWx5JFRhqeYEG9J5qQBugSlU1-MP2JFaoxz9igz4mh2qF59mkQRdp8ctZtjwebuVpTV7uFIdrYtL79Zxv8rzYF2W53f3DfADQ402J</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation</title><source>esp@cenet</source><creator>HENDRIKUS JOHANNES BERNARDUS PETERS ; WALTER PETER DE MUNNIK</creator><creatorcontrib>HENDRIKUS JOHANNES BERNARDUS PETERS ; WALTER PETER DE MUNNIK</creatorcontrib><description>Chip Scale Packages - CSPs - have the electronic circuits on a silicon chip (6). Electrical contact with the chip is made via bump contact points (7) under the chip and above the base carrier (4). After assembly, the package is encapsulated in insulating material. In conventional manufacturing systems, air can become trapped under the chip, leaving a void (8). In the present method a small vent hole is left in the center of the chip.</description><edition>7</edition><language>dut ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001106&DB=EPODOC&CC=NL&NR=1011949C2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001106&DB=EPODOC&CC=NL&NR=1011949C2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HENDRIKUS JOHANNES BERNARDUS PETERS</creatorcontrib><creatorcontrib>WALTER PETER DE MUNNIK</creatorcontrib><title>Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation</title><description>Chip Scale Packages - CSPs - have the electronic circuits on a silicon chip (6). Electrical contact with the chip is made via bump contact points (7) under the chip and above the base carrier (4). After assembly, the package is encapsulated in insulating material. In conventional manufacturing systems, air can become trapped under the chip, leaving a void (8). In the present method a small vent hole is left in the center of the chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjTEOwjAQBNNQIOAPRw8SAZrUEYgCqOjRxbkkFs6dZZ_hEXyaoPAAqpV2Z7TT7H1BTg0aTcFyCz1pJzU0EoAcGQ3C1oDprIdo0BF4NA9saQUpUoTYo3MgnvgrWx5JFRhqeYEG9J5qQBugSlU1-MP2JFaoxz9igz4mh2qF59mkQRdp8ctZtjwebuVpTV7uFIdrYtL79Zxv8rzYF2W53f3DfADQ402J</recordid><startdate>20001106</startdate><enddate>20001106</enddate><creator>HENDRIKUS JOHANNES BERNARDUS PETERS</creator><creator>WALTER PETER DE MUNNIK</creator><scope>EVB</scope></search><sort><creationdate>20001106</creationdate><title>Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation</title><author>HENDRIKUS JOHANNES BERNARDUS PETERS ; WALTER PETER DE MUNNIK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_NL1011949CC23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>dut ; eng</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HENDRIKUS JOHANNES BERNARDUS PETERS</creatorcontrib><creatorcontrib>WALTER PETER DE MUNNIK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HENDRIKUS JOHANNES BERNARDUS PETERS</au><au>WALTER PETER DE MUNNIK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation</title><date>2000-11-06</date><risdate>2000</risdate><abstract>Chip Scale Packages - CSPs - have the electronic circuits on a silicon chip (6). Electrical contact with the chip is made via bump contact points (7) under the chip and above the base carrier (4). After assembly, the package is encapsulated in insulating material. In conventional manufacturing systems, air can become trapped under the chip, leaving a void (8). In the present method a small vent hole is left in the center of the chip.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | dut ; eng |
| recordid | cdi_epo_espacenet_NL1011949CC2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T13%3A42%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HENDRIKUS%20JOHANNES%20BERNARDUS%20PETERS&rft.date=2000-11-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ENL1011949CC2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |